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Extra resources for Introduction to Digital Electronics (Essential Electronics Series)
The bubble on the output of the N O R gate indicates this second interpretation of the gate's operation since it signifies the output is 0 when either of the inputs is 1. Regarding positive and negative assertion level logic, a non-bubbled input or output indicates a 1 being input or output (positive level logic) whilst a 0 indicates a 0 being input or output (negative level logic). In the case of the NOR operator such assertion level logic indicates that Y is active-LOW (gives a 0) when either A OR B is active-HIGH (an input of 1).
01000 - 5 -00101 ~ +11011 +3 100011 The fifth bit is the sign bit (it is 0 for the binary codes of + 8 and + 5, but 1 (indicating a complemented number) f o r - 5). Since it is 0 in the answer this shows that the result is positive, with a binary value of 0011 = 3~0. The 'overflow' sixth bit in the result is discarded. 26 Subtract 8 from 5 using binary notation. Solution 5 00101 two's Comp. 00101 - 8 -01000 ~ +11000 -3 11101 Again, the fifth bit is the sign bit which since it is 1 indicates the result is negative.
Then letting A - X, B - Y, C - Z gives" x+(Y. z ) - ( x + ~9- (x+z) which has the same form as the second equation. 24 m What is the dual of Y= A. 4? Duality and gate equivalence 21 Solution The circuit to implement Y and its dual are shown in Fig. 16. This gives _ _ r : A + (A- 8) Using Boolean algebra: Y - A -(A + B) inverting both sides = A +(A + B) De Morgan's theorem = A + A 9B De Morgan's theorem Hence Y = A + A 9B as above. 211, as expected due to duality. AB. AT B A Fig. (B+C) and produce alternative representations of it using only a three-input A N D and three-input OR gate (assuming NOT gates are also available).
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