Download Fully-Depleted SOI CMOS Circuits and Technology for by Takayasu Sakurai PDF

By Takayasu Sakurai

An important factor confronting CMOS know-how is the facility explosion of chips coming up from the scaling legislation. Fully-depleted (FD) SOI know-how presents a promising low-power approach to chip implementation. Ultralow-power VLSIs, that have an influence intake of below 10 mW, should be key elements of terminals within the coming ubiquitous-IT society. Fully-Depleted SOI CMOS Circuits and expertise for Ultralow-Power purposes addresses the matter of decreasing the availability voltage of traditional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit layout for FD-SOI units at a provide voltage of half V.

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Extra resources for Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications

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Since there is no punch-through current when the Si film is thin enough, the FD type can be scaled down to make the channel region shorter just by thinning the Si film. So, there is no need to dope the Si film; and one of the intrinsic properties of undoped Si is a high electron mobility. Moreover, since the gate potential provides good control of the channel potential, the subthreshold slope is steeper than in the PD-type, making low-voltage operation possible. PD type FD type Fig. 17 Two-dimensional electron potential in PD- and FD-SOI MOSFETs.

ED-37, No. 9, pp. 2015-2021, 1990. 13] C. Jaussaud, J. Margail, J. Stoemenos, and M. Bruel, “High Temperature Annealing of SIMOX Layers, Physical Mechanism of Oxygen Segregation,” Proceedings of Mat. Res. Soc. , Vol. 107, p. 17, 1988. 14] S. Nakashima and K. , Vol. 26, No. 20, pp. 1647-1649, 1990. 15] S. Nakashima, T. Katayama, Y. Miyamura, A. Matsuzaki, M. Imai, K. Izumi, and N. Ohwada, “Thickness Increment of Buried Oxide in a SIMOX Wafer by High-Temperature Oxidation,” Proceedings 1994 IEEE International SOI Conference, pp.

Fig. 16 Energy band diagrams for PD- and FD-SOI MOSFETs. EF denotes the Fermi energy of the source. 11]. The potential barrier to holes between the body and the source is lower in the FD type. As a result, hardly any holes accumulate in the body (Fig. 17), which mitigates floating-body effects. In addition, the surface electric field is weak, which enhances carrier mobility. Since there is no punch-through current when the Si film is thin enough, the FD type can be scaled down to make the channel region shorter just by thinning the Si film.

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