By Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng
This booklet offers huge and finished assurance of the full EDA movement. EDA/VLSI practitioners and researchers short of fluency in an "adjacent" box will locate this a useful connection with the elemental EDA recommendations, ideas, facts buildings, algorithms, and architectures for the layout, verification, and try of VLSI circuits. an individual who must study the innovations, ideas, info buildings, algorithms, and architectures of the EDA stream will take advantage of this book.Covers whole spectrum of the EDA movement, from ESL layout modeling to logic/test synthesis, verification, actual layout, and try out - is helping EDA rookies to get "up-and-running" quick comprises finished insurance of EDA techniques, rules, info buildings, algorithms, and architectures - is helping all readers enhance their VLSI layout competence includes most up-to-date developments no longer but on hand in different books, together with try compression, ESL layout modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - is helping readers to design/develop testable chips or items comprises best-practices anywhere applicable in so much chapters - is helping readers keep away from expensive errors
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Extra info for Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)
The result has been numerous approaches and algorithms for physical design automation [Preas 1988; Gerez 1998; Sait 1999; Sherwani 1999; Scheffer 2006a, 2006b]. 4. 4 Typical physical design flow. 5 Typical EDA flow. 5, which begins with modeling and design verification. This implies a recursive process with debugging until the resultant models reach a level of detail that can be processed by logic synthesis. As a result of current EDA capabilities, the design process is highly automated from this point.
Testbenches are behavioral models that emulate the surrounding system environment to provide input stimuli to the design under test and process the output responses during simulation. RTL models of the detailed design are then developed and verified with the same testbenches that were used for verification of the architectural design, in addition to testbenches that target design errors in the RTL description of the design. With sufficient design verification at this point in the design process, functional vectors can be captured in the RTL simulation and then used for subsequent simulations (regression testing) of the more detailed levels of design, including synthesized gate-level design, transistor-level design, and physical design.
Wang’s work in at-speed scan testing, test compression, and logic BIST has proved crucial to ensuring the quality and testability of nanometer designs, and his inventions are gaining industry acceptance for use in designs manufactured at the 90-nanometer scale and below. He spearheaded efforts to raise endowed funds in memory of his NTU chair professor, Dr. Irving T. Ho, cofounder of the Hsinchu Science Park and vice chair of the National Science Council, Taiwan. Since 2003, he has helped establish a number of chair professorships, graduate fellowships, and undergraduate scholarships at Stanford University, National Taiwan University and National Tsing Hua University in Taiwan, as well as Xiamen University, Tsinghua University, and Shanghai Jiaotong University in China.
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