Download EC1258 Digital Electronics Laboratory Manual-REC(2) PDF

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59 FUNCTION TABLE: S1 0 0 1 1 S0 0 1 0 1 INPUT X → D0 = X S1’ S0’ X → D1 = X S1’ S0 X → D2 = X S1 S0’ X → D3 = X S1 S0 Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0 LOGIC DIAGRAM FOR DEMULTIPLEXER: 2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 60 TRUTH TABLE: S1 INPUT S0 I/P D0 OUTPUT D1 D2 2007-08/Even/IV/ECE/EC1258/DE/LM D3 Page No. 61 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 PIN DIAGRAM FOR IC 74150: PIN DIAGRAM FOR IC 74154: 2007-08/Even/IV/ECE/EC1258/DE/LM Page No.

COMPONENT AND GATE X-OR GATE OR GATE NOT GATE 4-BIT MAGNITUDE COMPARATOR IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 IC 7485 QTY. 2 1 1 1 2 - 1 30 THEORY: The comparison of two numbers is an operator that determine one number is greater than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determine their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B (or) A

38 LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR 2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 39 TRUTH TABLE: Input Data A Input Data B Addition Subtraction A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 2007-08/Even/IV/ECE/EC1258/DE/LM 1 1 0 Page No. 40 LOGIC DIAGRAM: BCD ADDER K MAP Y = S4 (S3 + S2) 2007-08/Even/IV/ECE/EC1258/DE/LM Page No.

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